The present invention relates to a semiconductor memory device, particularly one with a memory cell organization suitable for higher integration.
An example of a memory cell organization of a highely integrated dynamic semiconductor memory device as proposed in the lecture Number FAM 17.4 of ISSCC 85 is shown in FIGS. 1A and 1B. As illustrated, it comprises a p-type semiconductor substrate 1, a field oxide film 2, a first poly-silicon layer 3, a capacitor insulating film 4, an n.sup.+ diffusion layer 5, a first Al interconnection layer 6 forming bit lines and a second poly-silicon layer 7 forming word lines 9. Although not illustrated as such, the second poly-silicon layer 7 is electrically connected at regular intervals with the second Al interconnection layer 8 to reduce the effective resistance of the word line 9. Contact holes 10 are for electrical connection of the first Al interconnection layer 6 to the n.sup.+ diffusion layer 5. Cp represents a data charge storage capacitance formed of the poly-silicon 3 and the n.sup.+ diffusion layer 5 on the respective sides of the capacitor insulating film 4, on the sidewall of an isolation trench. Cf represents a data charge storage capacitor formed of the poly-silicon 3 and the n.sup.+ diffusion layer 5 on the respective sides of the capacitor insulating film 4, on the flat part.
By utilizing the sidewall of the isolation trench for forming a data charge storage capacitance Cp, the area for the data charge storage capacitance Cf on the flat part can be reduced. As a result, the reduction in the chip area does not lead to reduction in operation margin and makes it possible to provide data storage capacitance for securing the stored data charge against minority carriers injected because of radiation such as alpha particles. As longer periphery of the memory cells is utilized, the trench may be made shallower to obtain the same data charge storage capacitance Cp+Cf.
In a conventional highly-integrated dynamic semiconductor memory of a folded-bit line configuration and having the above-described memory cells in which data charge storage capacitance are formed on sidewalls of the isolation trenches, an area necessary for forming each memory cell (for one bit) comprises an area for 1/2 contact hole (one contact is shared by two memory cells) and an area for two word lines. However, where the data charge storage capacitance Cp on the sidewalls of the isolation trenches are enlarged by forming deep isolation trenches to reduce the data charge storage capacitances Cf on the flat part in an attempt to increase the degree of integration, it then becomes difficult to secure the area for disposing two word lines. Thus, a restriction on the designing is imposed.